or_integration_tests(
  "dbSta"
  TESTS
    block_sta1
    clock_pin
    constant1
    find_clks1
    find_clks2
    hier2
    hierclock
    hierwrite
    make_port
    network_edit1
    power1
    read_liberty1
    read_verilog1
    read_verilog2
    read_verilog3
    read_verilog4
    read_verilog5
    read_verilog6
    read_verilog7
    read_verilog8
    read_verilog9
    read_verilog10
    read_verilog10_no_prop
    read_verilog11
    readdb_hier
    report_cell_usage
    report_cell_usage_file
    report_cell_usage_modinsts
    report_cell_usage_modinsts_metrics
    report_cell_usage_physical_only
    report_json1
    report_timing_histogram
    report_logic_depth_histogram
    sdc_get1
    sdc_names1
    sdc_names2
    sta1
    sta2
    sta3
    sta4
    sta5
    write_sdc1
    write_verilog1
    write_verilog2
    write_verilog3
    write_verilog4
    write_verilog5
    write_verilog6
    write_verilog7
    write_verilog8
)

if(ENABLE_TESTS)
  add_subdirectory(cpp)
endif()
